1. Field of Invention
The present invention relates to an integrated circuit and, more particularly, to a method for preventing electrostatic discharge failure in an integrated circuit package.
2. Description of the Related Art
Very Large-Scale Integration (VLSI) allows manufacturers to produce integrated circuits (IC) with smaller dimensions, higher density and increased power and performance. With the increased power and performance these circuit packages are able to handle an increasing number of input/output signals that result from the increased integration of circuit functions. To support these increased functions and signals, additional terminals are provided for the IC. These additional signals are electrically connected to the IC through connector pins connected to the terminals.
IC packages are an interconnected array of active and passive components, which are capable of performing a complete circuit function, fabricated on a single crystal of semiconductor material (usually silicon). IC packages are constructed in a variety of package types which contain the circuit. During the packaging process, a lead frame provides the pins for making connections to an external circuit.
As the functions and number of pins on IC packages has increased with a decrease in the size of the IC package, the pin pitch on the IC package has rapidly decreased. Pin pitch is a recognized term of art which is defined as the distance of pins of an IC center-to-center. This decreased pin pitch increases the possibility of circuit failure due to electrostatic discharge (ESD) between pins.
ESD is considered a major reliability threat of integrated circuit technologies. The possibility of ESD failure involving non-wired pins has been considered. Matsunoto et al., discloses in the reference, New Failure Mechanism due to Non-Wired Pin ESD Stressing, that ESD failure can occur due to discharge through the resin of an IC package from non-wired pins to wired pins. Narrow pin or lead pitches may increase the electric field during non-wired pin ESD stressing so as to degrade ESD immunity of the non-wired pins. The breakdown of resin or other materials, which allows ESD current discharge from a non-wired pin to an adjacent wired pin, is determined by the strength of the electric field between the pins. Matsumoto et al. concludes that even when ESD stressing is low, discharge can occur when ESD stress is repeatedly applied to the non-wired pin. As a result, increased discharge current flows into the adjacent wired pin and destroys the adjacent wired pin.
U.S. Pat. No. 5,712,753 to Yeh et al. discloses a method to prevent electrostatic discharge failure in an integrated circuit package by means of electrically connecting a non-wired pin to a wired pin on the integrated circuit package. The wired pin is in turn connected to an electrostatic discharge protection circuit. Thus, the integrated circuit package prevents electrostatic discharge stressing of the non-wired pin.
U.S. Pat. No. 5,715,127 to Yu also discloses a method to prevent electrostatic discharge failure in an integrated circuit package. Yu discloses electrically connecting the non-wired pins to a metal lead frame of the package. The metal lead frame is connected to a bonding pad which in turn is connected to an electrostatic discharge protection circuit. This construction is intended to prevent ESD failure due to non-wired pin stressing.
One disadvantage of both prior art preventive methods is that it is necessary to provide additional ESD protection circuitry in the integrated circuit design. As minimization of circuit size and complexity is a goal of circuit design, it would be desirable to provide a means to prevent the problem of ESD failure without the need of additional circuitry.